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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - n o v . , 2 0 1 2 a p w 7 0 7 3 a w w w . a n p e c . c o m . t w 1 the apw7073a is a voltage mode and synchronous pwm controller which drives dual n-channel mosfets. the device integrates all of the controlling, monitoring, and protecting functions into a single package, and pro- vides one controlled power output with over-current protection. t h e a p w 7 0 7 3 a p r o v i d e s e x c e l l e n t r e g u l a t i o n f o r o u t p u t l o a d v a r i a t i o n . t h e i n t e r n a l 0 . 6 v t e m p e r a t u r e - c o m p e n - s a t e d r e f e r e n c e v o l t a g e i s d e s i g n e d t o m e e t t h e r e q u i r e - m e n t o f l o w o u t p u t v o l t a g e a p p l i c a t i o n s . t h e d e v i c e i n - c l u d e s a 2 0 0 k h z f r e e - r u n n i n g t r i a n g l e - w a v e o s c i l l a t o r t h a t i s a d j u s t a b l e f r o m 5 0 k h z t o 1 0 0 0 k h z . the apw7073a has been equipped with excellent pro- tection functions: power-on-reset (por) and over-cur- rent protection (ocp). the por circuit can monitor the vcc, en, and ocset voltages to make sure the supply voltages exceed their threshold voltage while the con- troller is running. the ocp monitors the output current by using the voltage drop across the upper mosfet?s r ds (on) . when the output current reaches the trip point, the ic shuts off the converter and initiates a new soft-start process. after two over-current events are counted, the device turns off both high-side and low-side mosfets and the converter output is latched to be floating. it re- quires a por of vcc to restart. dc-dc power supply s y n c h r o n o u s b u c k p w m c o n t r o l l e r single 12v power supply required 0.6v reference with 1% accuracy shutdown and soft-start function programmable frequency range from 50 khz to 1000khz voltage mode pwm control design up to 100% duty cycle over-current protection (ocp) s o p - 1 4 p a c k a g e l e a d f r e e a n d g r e e n d e v i c e s a v a i l a b l e ( r o h s c o m p l i a n t ) f e a t u r e s a p p l i c a t i o n s g e n e r a l d e s c r i p t i o n t y p i c a l a p p l i c a t i o n c i r c u i t v out 12v v in apw7073a c ss r ocset l r fs a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . p i n c o n f i g u r a t i o n gnd 7 fb 5 ocset 2 8 phase ss 3 en 6 comp 4 14 vcc 10 boot 13 pvcc 9 ugate 12 lgate 11 pgnd rt 1 sop-14
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - n o v . , 2 0 1 2 a p w 7 0 7 3 a w w w . a n p e c . c o m . t w 2 apw7073a handling code temperature range package code apw7073a k : apw7073a xxxxx xxxxx - date code assembly material package code k : sop - 14 operating ambient temperature range e : -20 to 70 c handling code tr : tape & reel assembly material l : lead free device g : halogen and lead free device a b s o l u t e m a x i m u m r a t i n g s (note 1) symbol parameter rating unit v cc , v pvcc vcc , pvcc to gnd - 0.3 to +16 v v boot boot to phase - 0.3 to +16 v v ugate ugate to phase <400ns pulse width >400ns pulse width - 5 to v boot +5 - 0.3 to v boot +0.3 v v lgate lgate to p gnd <400ns pulse width >400ns pulse width - 5 to v pvcc +5 - 0.3 to v pvcc +0.3 v v phase phase to gnd <400ns pulse width >400ns pulse width - 10 to +30 - 0.3 to 16 v v rt, v ocset, v en rt, ocset, en to gnd - 0.3 to v cc +0.3 v v fb, v comp , v ss f b, comp, ss to gnd - 0.3 to 7 v v pgnd pgnd to gnd - 0.3 to +0.3 v t j junction temperature range - 20 to 150 c t stg storage temperature - 65 to 150 c t sdr maximum lead soldering temperature , 10 seconds 260 c n o t e 1 : s t r e s s e s b e y o n d t h o s e l i s t e d u n d e r " a b s o l u t e m a x i m u m r a t i n g s " m a y c a u s e p e r m a n e n t d a m a g e t o t h e d e v i c e . t h e s e a r e s t r e s s r a t i n g s o n l y a n d f u n c t i o n a l o p e r a t i o n o f t h e d e v i c e a t t h e s e o r a n y o t h e r c o n d i t i o n s b e y o n d t h o s e i n d i c a t e d u n d e r " r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s " i s n o t i m p l i e d . e x p o s u r e t o a b s o l u t e m a x i m u m r a t i n g c o n d i t i o n s f o r e x t e n d e d p e r i o d s m a y a f f e c t d e v i c e r e l i a b i l i t y . symbol parameter typical value unit q ja junction - to - ambient thermal resistance in free air sop - 14 160 o c/w t h e r m a l c h a r a c t e r i s t i c s (note 2) o r d e r i n g a n d m a r k i n g i n f o r m a t i o n n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 c f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . note2: q ja is measured with the component mounted on a high effective the thermal conductivity test board in free air. the exposed pad of package is soldered directly on the pcb.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - n o v . , 2 0 1 2 a p w 7 0 7 3 a w w w . a n p e c . c o m . t w 3 symbol parameter rating unit v cc , v pvcc ic supply voltage 10.8 to 13.2 v v in converter input voltage 2.2 to 13.2 v v out converter output voltage 0.6 to 5 v i out converter output current 0 to 30 a t a ambient temperature range - 20 to 70 c t j junction temperature range - 20 to 125 c e l e c t r i c a l c h a r a c t e r i s t i c s u n l e s s o t h e r w i s e s p e c i f i e d , t h e s e s p e c i f i c a t i o n s a p p l y o v e r v c c = 1 2 v , a n d t a = - 2 0 ~ 7 0 c . t y p i c a l v a l u e s a r e a t t a = 2 5 c . apw70 73a symbol parameter test conditions min . typ . max . unit input supply current vcc supply current (shutdown mode) ugate, lgate and en = gnd - 0.5 1 ma i cc vcc supply current ugate and lgate open - 5 10 ma power - on - reset rising vcc threshol d 9 9.5 10.0 v falling vcc threshold 7.5 8 8.5 v rising v ocset threshold - 1.3 - v vocset hysteresis voltage - 0.1 - v rising en threshold voltage - 1.3 - v en hysteresis voltage - 0.1 - v oscillator accuracy - 15 - +15 % f osc free runn ing frequency rt = open - 200 - khz adjustment range rt pin: resistor to gnd; resistor to vcc 50 - 1000 khz v osc ramp amplitude (nominal 1.35v to 2.95 v) - 1 . 6 - v duty duty cycle range 0 - 100 % reference v ref reference voltage - 0. 6 0 - v refere nce voltage tolerance - 1 - +1 % pwm e rr or amplifier gain open loop gain r l = 10k, c l = 10p f (n ote 3) - 88 - db gbwp open loop bandwidth r l = 10k, c l = 10p f (note3) - 15 - mhz sr slew rate r l = 10k, c l = 10p f (note3) - 6 - v/ m s fb input current v fb = 0. 6 v - 0.1 1 m a v com p comp high voltage - 5.5 - v v com p comp low voltage - 0 - v i comp comp source current v com p = 2v - 5 - ma i comp comp sink current v com p = 2v - 5 - ma r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - n o v . , 2 0 1 2 a p w 7 0 7 3 a w w w . a n p e c . c o m . t w 4 e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) u n l e s s o t h e r w i s e s p e c i f i e d , t h e s e s p e c i f i c a t i o n s a p p l y o v e r v c c = 1 2 v , a n d t a = - 2 0 ~ 7 0 c . t y p i c a l v a l u e s a r e a t t a = 2 5 c . apw70 73a symbol parameter test conditions min . typ . max . unit gate drivers i ugate upper gate source current v boot = 12 v, v ugate - v phase = 2 v - 2.6 - a r ugate upper gate sink impedance v boot = 12v, i ugate = 0. 1 a - 1.6 2.4 w i l gate low er gate source current v pvcc = 12 v, v l gate = 2 v - 3.0 - a r lgate lower gate sink impedance v pvcc = 12v, i l gate = 0. 1 a - 1.25 1.8 8 w t d dead time - 50 - n s protection i ocset ocset source current v ocset = 11 .5v 1 7 0 200 2 5 0 m a enable/ soft - start i ss soft - star t charge current 24 30 36 m a n o t e 3 : g u a r a n t e e d b y d e s i g n
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - n o v . , 2 0 1 2 a p w 7 0 7 3 a w w w . a n p e c . c o m . t w 5 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s switching frequency(khz) j u n c t i o n t e m p e r a t u r e ( c ) s w i t c h i n g f r e q u e n c y v s . j u n c t i o n t e m p e r a t u r e reference voltage(v) j u n c t i o n t e m p e r a t u r e ( c ) r e f e r e n c e v o l t a g e v s . j u n c t i o n t e m p e r a t u r e -40 -20 0 20 40 60 80 100 120 180 185 190 195 200 205 0.594 0.595 0.596 0.597 0.598 0.599 0.6 0.601 0.602 -40 -20 0 20 40 60 80 100 120 o p e r a t i n g w a v e f o r m s v cc =12v, vin =12v v out =1.5v, l=1uh v cc =12v, vin =12v v out =1.5v, l=1uh p o w e r o n p o w e r o f f 1 1 2 2 1 1 2 2 3 3 3 3 c h 1 : v c c ( 5 v / d i v ) c h 2 : v s s ( 2 v / d i v ) c h 3 : v o u t ( 1 v / d i v ) t i m e : 1 0 m s / d i v c h 1 : v c c ( 5 v / d i v ) c h 2 : v s s ( 2 v / d i v ) c h 3 : v o u t ( 1 v / d i v ) t i m e : 2 m s / d i v
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - n o v . , 2 0 1 2 a p w 7 0 7 3 a w w w . a n p e c . c o m . t w 6 o p e r a t i n g w a v e f o r m s ( c o n t . ) e n ( v e n = v c c ) s h u t d o w n ( v e n = v g n d ) 1 1 2 2 1 1 2 2 c h 1 : v e n ( 5 v / d i v ) c h 2 : v s s ( 5 v / d i v ) c h 3 : v o u t ( 1 v / d i v ) t i m e : 1 0 m s / d i v 3 3 3 3 c h 1 : v e n ( 5 v / d i v ) c h 2 : v s s ( 5 v / d i v ) c h 3 : v o u t ( 1 v / d i v ) t i m e : 1 0 m s / d i v v cc =12v, vin =12v v out =1.5v, l=1uh v cc =12v, vin =12v v out =1.5v, l=1uh u g a t e r i s i n g u g a t e f a l l i n g 1 1 2 2 1 1 2 2 3 3 3 3 c h 1 : v u g a t e ( 2 0 v / d i v ) c h 2 : v l g a t e ( 5 v / d i v ) c h 3 : v p h a s e ( 1 0 v / d i v ) t i m e : 5 0 n s / d i v c h 1 : v u g a t e ( 2 0 v / d i v ) c h 2 : v l g a t e ( 5 v / d i v ) c h 3 : v p h a s e ( 1 0 v / d i v ) t i m e : 5 0 n s / d i v v cc =12v, vin =12v v out =1.5v, l=1uh v cc =12v, vin =12v v out =1.5v, l=1uh
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - n o v . , 2 0 1 2 a p w 7 0 7 3 a w w w . a n p e c . c o m . t w 7 o p e r a t i n g w a v e f o r m s ( c o n t . ) l o a d t r a n s i e n t r e s p o n s e s h o r t t e s t b e f o r e p o w e r o n 1 1 2 2 1 1 2 2 3 3 4 4 c h 1 : v o u t ( 5 0 0 m v / d i v ) c h 4 : i o u t ( 5 a / d i v ) t i m e : 2 0 0 m s / d i v v cc =12v, vin =12v v out =1.5v, l=1uh c h 1 : v s s ( 5 v / d i v ) c h 2 : i l ( 1 0 a / d i v ) c h 3 : v o u t ( 1 v / d i v ) c h 4 : v u g a t e ( 2 0 v / d i v ) t i m e : 2 0 m s / d i v s h o r t t e s t a f t e r p o w e r o n 1 1 2 2 3 3 c h 1 : v s s ( 5 v / d i v ) c h 2 : i l ( 1 0 a / d i v ) c h 3 : v o u t ( 1 v / d i v ) c h 4 : v u g a t e ( 2 0 v / d i v ) t i m e : 2 0 m s / d i v 4 4 v cc =12v, v in =12v, v out =1.5v, l=1 m h, r ocset = 1k w , r ds(on) = 8.5m w v cc =12v, v in =12v, v out =1.5v, l=1 m h, r ocset = 1k w , r ds(on) = 8.5m w
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - n o v . , 2 0 1 2 a p w 7 0 7 3 a w w w . a n p e c . c o m . t w 8 f u n c t i o n p i n d e s c r i p t i o n v c c p o w e r s u p p l y i n p u t p i n . c o n n e c t a n o m i n a l 1 2 v p o w e r s u p p l y t o t h i s p i n . t h e p o w e r - o n - r e s e t f u n c t i o n m o n i t o r s t h e i n p u t v o l t a g e b y t h i s p i n . i t i s r e c o m m e n d e d t h a t a d e c o u p l i n g c a p a c i t o r ( 1 t o 1 0 m f ) b e c o n n e c t e d t o t h e g n d f o r n o i s e d e c o u p l i n g . p v c c t h i s p i n p r o v i d e s a s u p p l y v o l t a g e f o r t h e l o w e r g a t e d r i v e . c o n n e c t t h i s p i n t o v c c p i n i n n o r m a l u s e . b o o t t h i s p i n p r o v i d e s t h e b o o t s t r a p v o l t a g e t o t h e u p p e r g a t e d r i v e r f o r d r i v i n g t h e n - c h a n n e l m o s f e t . p h a s e t h i s p i n i s t h e r e t u r n p a t h f o r t h e u p p e r g a t e d r i v e r . c o n n e c t t h i s p i n t o t h e u p p e r m o s f e t s o u r c e . t h i s p i n i s a l s o u s e d t o m o n i t o r t h e v o l t a g e d r o p a c r o s s t h e m o s f e t f o r o v e r - c u r r e n t p r o t e c t i o n . g n d t h i s p i n i s t h e s i g n a l g r o u n d p i n . c o n n e c t t h e g n d t o a g o o d g r o u n d p l a n e . p g n d t h i s p i n i s t h e p o w e r g r o u n d p i n f o r t h e l o w e r g a t e d r i v e r . i t s h o u l d b e t i e d t o t h e g n d o n t h e b o a r d . c o m p t h i s p i n i s t h e o u t p u t o f p w m e r r o r a m p l i f i e r . i t i s u s e d t o s e t t h e c o m p e n s a t i o n c o m p o n e n t s . f b t h i s p i n i s t h e i n v e r t i n g i n p u t o f t h e p w m e r r o r a m p l i f i e r . i t i s u s e d t o s e t t h e o u t p u t v o l t a g e a n d t h e c o m p e n s a t i o n c o m p o n e n t s . u g a t e t h i s p i n i s t h e g a t e d r i v e r f o r t h e u p p e r m o s f e t o f p w m o u t p u t . l g a t e t h i s p i n i s t h e g a t e d r i v e r f o r t h e l o w e r m o s f e t o f p w m o u t p u t . s s c o n n e c t a c a p a c i t o r t o t h e g n d a n d a 3 0 m a c u r r e n t s o u r c e c h a r g e s t h i s c a p a c i t o r t o s e t t h e s o f t - s t a r t t i m e . o c s e t t h i s p i n s e r v e s t w o f u n c t i o n s : a s h u t d o w n c o n t r o l a n d t h e s e t t i n g o f o v e r c u r r e n t l i m i t t h r e s h o l d . p u l l i n g t h i s p i n b e l o w 1 . 3 v w i l l s h u t d o w n t h e c o n t r o l l e r , f o r c i n g t h e u g a t e a n d l g a t e s i g n a l s t o b e l o w . a r e s i s t o r ( r o c s e t ) c o n n e c t e d b e t w e e n t h i s p i n a n d t h e d r a i n o f t h e h i g h s i d e m o s f e t w i l l d e t e r m i n e t h e o v e r c u r r e n t l i m i t . a n i n t e r n a l 2 0 0 m a c u r r e n t s o u r c e w i l l f l o w t h r o u g h t h i s r e s i s t o r , c r e a t i n g a v o l t a g e d r o p , w h i c h w i l l b e c o m p a r e d w i t h t h e v o l t a g e a c r o s s t h e h i g h s i d e m o s f e t . t h e t h r e s h o l d o f t h e o v e r c u r r e n t l i m i t i s t h e r e f o r e g i v e n b y : e n p u l l t h i s p i n a b o v e 1 . 3 v t o e n a b l e t h e d e v i c e a n d p u l l t h i s p i n b e l o w 1 . 2 v t o d i s a b l e t h e d e v i c e . i n s h u t d o w n , t h e s s i s d i s c h a r g e d a n d t h e u g a t e a n d l g a t e p i n s a r e h e l d l o w . n o t e t h a t d o n ? t l e a v e t h i s p i n o p e n . r t t h i s p i n a l l o w s a d j u s t i n g t h e s w i t c h i n g f r e q u e n c y . c o n n e c t a r e s i s t o r f r o m r t p i n t o t h e g r o u n d t o i n c r e a s e t h e s w i t c h i n g f r e q u e n c y . c o n v e r s e l y , c o n n e c t a r e s i s t o r f r o m r t t o t h e v c c t o d e c r e a s e t h e s w i t c h i n g f r e q u e n c y . ds(on) ocset ocset peak r r i i = ) ua 200 (
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - n o v . , 2 0 1 2 a p w 7 0 7 3 a w w w . a n p e c . c o m . t w 9 b l o c k d i a g r a m t y p i c a l a p p l i c a t i o n c i r c u i t v out vcc boot ugate phase pvcc lgate pgnd gnd ocset fb ss en 12v v in comp 3k 1nf 0.1 m f apm2510 apm2556 1 m f 0.1 m f 1n4148 1500 m fx2 7.2 m h 1.8k 8.2k 1nf 2.2 3.3k 10nf 1nf 10nf 3.3k on off rt zener 15v 10 m f 10 m f 1 m f nc nc 5.1 1 m f 2200 m fx2 apm2556 apm2510 2.2 2.2 2.2 gate control oscillator soft - start power-on - reset phase lgate rt fb ss gnd en vcc ocset boot ugate pgnd pvcc i ocset 200 m a o.c.p comparator error amp pwm comparator comp sawtooth wave v ref 15k 15k i ss 30 m a
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - n o v . , 2 0 1 2 a p w 7 0 7 3 a w w w . a n p e c . c o m . t w 1 0 f u n c t i o n d e s c r i p t i o n power-on-reset (por) the power-on-reset (por) function of apw7073a continu- ally monitors the input supply voltage (v cc ), the enable (en) pin, and the ocset pin. the supply voltage (v cc ) must exceed its rising por threshold voltage. the volt- age at ocset pin is equal to v in less a fixed voltage drop (v ocset = v in - v rocset ). the en pin can be pulled high with connecting a resistor to the vcc. the por function initiates soft-start operation after vcc , en, and ocset voltages exceed their por thresholds. for op- eration with a single +12v power source, v in and v cc are equivalent and the +12v power source must exceed the rising vcc threshold. the por function inhibits opera- tion at disabled status (en pin low). with both input sup- plies above their por thresholds, the device initiates a soft-start interval. soft-start/en the ss/en pins control the soft-start and enable or disable the controller. connect a soft-start capacitor from ss pin to gnd to set the soft-start interval. figure1. shows the soft-start interval. when v cc reaches its power- on-reset threshold (9.5v), internal 30 m a current source starts to charge the capacitor. when the v ss reaches the enabled threshold about 1.8v, the internal 0.6v reference starts to rise and follows the v ss ; the error amplifier output (v comp ) suddenly raises to 1.35v, which is the valley of the triangle wave of the oscillator, leads the v out to start-up. until the v ss reaches about 4.2v, the internal reference completes the soft-start interval and reaches to 0.6v, and then v out is in regulation. the ss still rises to 5.5v and then stops. figure 1. soft-start internal where: c ss = external soft-start capacitor i ss = soft-start current=30 m a over-current protection (monitor upper mosfet) the apw7073a monitors the voltage across the upper mosfet and uses the ocset pin to set the over-current trip point. a resistor (r ocset ) connected between ocset pin and the drain of the upper mosfet will determine the over current limit. an internal 200 m a current source will flow through this resistor, creating a voltage drop, which will be compared with the voltage across the upper mosfet. when the voltage across the upper mosfet exceeds the voltage drop across the r ocset , an over-current will be detected. the threshold of the over current limit is therefore given by: for the over-current, it is never occurred in the normal operating load range; the variation of all parameters in the above equation should be determined. - the mosfet?s r ds(on) is varied by temperature and gate to source voltage, the user should determine the maximum r ds(on) in manufacturer?s datasheet. - the minimum i ocset (170 m a) and minimum r ocset should be used in the above equation. - note that the i limit is the current flow through the upper mosfet; i limit must be greater than maximum output current add the half of inductor ripple current. v 4 . 2 i c t t t ss ss 1 2 start soft = - = - 4.2v 1.8v t 1 t 2 t 0 voltage time v out v ss ( ) on ds ocset ocset limit r r i i =
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - n o v . , 2 0 1 2 a p w 7 0 7 3 a w w w . a n p e c . c o m . t w 1 1 an over current condition will shut down the device and discharge the c ss with a 30 m a sink current and then initiate the soft-start sequence. after two over-current events are counted, the device turns off both high-side and low-side mosfets and the converter output is latched to be floating. it requires a por of vcc to restart. f u n c t i o n d e s c r i p t i o n ( c o n t . ) over-current protection (cont.) figure 2. oscillator frequency vs. rt resistance figure 3. oscillator frequency vs. rt resistance (high frequency) rt resistance (k w ) frequency (khz) rt resistance (k w ) frequency (khz) 0 100 200 300 400 500 600 700 800 900 1000 10 1000 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 figure 4. oscillator frequency vs. rt resistance (low frequency) rt resistance (k w ) frequency (khz) 200 300 400 500 600 700 800 900 1000 50 70 90 110 130 150 170 switching frequency the apw7073a provides the oscillator switching fre- quency adjustment. the device includes a 200khz free- running triangle wave oscillator. if operating in higher frequency than 200khz, connect a resistor from rt pin to the ground to increase the switching frequency. conversely, if operating in lower frequency than 200khz, connect a resistor from rt to the vcc to decrease the switching frequency. figure 2. shows how to select the resistor for the desired frequency. figure 3 shows more detail for the higher frequencies and figure 4 shows the lower frequency detail.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - n o v . , 2 0 1 2 a p w 7 0 7 3 a w w w . a n p e c . c o m . t w 1 2 a p p l i c a t i o n i n f o r m a t i o n output voltage selection the output voltage can be programmed with a resistive divider. use 1% or better resistors for the resistive divider is recommended. the fb pin is the inverter input of the error amplifier , and the reference voltage is 0.6v . the output voltage is determined by: where r out is the resistor connected from v out to fb, and r gnd is the resistor connected from fb to gnd. output inductor selection the inductor value determines the inductor ripple current and affects the load transient response. higher inductor value reduces the inductor?s ripple current and induces lower output ripple voltage. the ripple current and ripple voltage can be approximated by: ? ? ? ? ? + = gnd out out r r 1 0.6 v where fs is the switching frequency of the regulator. although increase of the inductor value and frequency reduces the ripple current and voltage, a tradeoff will exist between the inductor?s ripple current and the regulator load transient response time. a smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. increasing the switching frequency (f s ) also reduces the ripple current and voltage, but it will increase the switching loss of the mosfet and the power dissipation of the converter. the maximum ripple current occurs at the maximum input voltage. a good starting point is to choose the ripple current to be approximately 30% of the maximum output current. once the inductance value has been chosen, select an inductor that is capable of carrying the required peak current without going into saturation. in some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. this will result in a larger output ripple voltage. in out s out in ripple v v l f v v i - = esr i v ripple out = d output capacitor selection higher capacitor value and lower esr reduce the output ripple and the load transient drop. therefore, selecting high performance low esr capacitors is intended for switch- ing regulator applications. in some applications, mul- tiple capacitors have to be parallelled to achieve the desired esr value. a small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors also must be considered. if tantalum capacitors are used, make sure they are surge tested by the manufactures. if in doubt, consult the capacitors manufacturer. input capacitor selection the input capacitor is chosen based on the voltage rating and the rms current rating. for reliable operation, select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. the maximum rms current rating requirement is approximately i out /2, where i out is the load current. during power up, the input capacitors have to handle large amount of surge current. if tantalum capacitors are used, make sure they are surge tested by the manufactures. if in doubt, consult the capacitors manufacturer. for high frequency decoupling, a ceramic capacitor 1 m f can be connected between the drain of upper mosfet and the source of lower mosfet. mosfet selection the selection of the n-channel power mosfets are determined by the r ds(on) , reverse transfer capacitance (c rss ) and maximum output current requirement. there are two components of loss in the mosfets: conduction loss and transition loss. for the upper and lower mosfet, the losses are approximately given by the fol- lowing equations: p upper = i out 2 ( 1+ tc)(r ds(on) )d + (0.5)( i out )(v in )( t sw )f s p lower = i out 2 (1+ tc)(r ds(on) )(1-d) where i out is the load current tc is the temperature dependency of r ds(on) f s is the switching frequency t sw is the switching interval d is the duty cycle
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - n o v . , 2 0 1 2 a p w 7 0 7 3 a w w w . a n p e c . c o m . t w 1 3 note that both mosfets have conduction loss while the upper mosfet includes an additional transition loss. the switching internal, t sw , is the function of the reverse transfer capacitance c rss . the (1+tc) term is to factor in the temperature dependency of the r ds(on) and can be extracted from the ?r ds(on) vs tempera ture? curve of the power mosfet. pwm compensation the output lc filter of a step down converter introduces a double pole, which contributes with -40db/decade gain slope and 180 degrees phase shift in the control loop. a compensation network among comp, fb, and v out should be added. the compensation network is shown in figure 8. the output lc filter consists of the output induc- tor and output capacitors. the transfer function of the lc filter is given by: a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) mosfet selection (cont.) the f lc is the double poles of the lc filter, and f esr is the zero introduced by the esr of the output capacitor. v phase l v out c out esr figure 5. the output lc filter figure 6. the lc filter gain and frequency the pwm modulator is shown in figure 7. the input is the output of the error amplifier and the output is the phase node. the transfer function of the pwm modula- tor is given by: out esr c esr 2 1 f p = f lc f esr -40db/dec -20db/dec frequency(hz) g a i n ( d b ) osc in pwm v v gain d = figure 7. the pwm modulator output of error amplifier g v osc pwm comparator driver driver phase v in osc the compensation network is shown in figure 8. it provides a close loop transfer function with the highest zero crossover frequency and sufficient phase margin. the transfer function of error amplifier is given by: the poles and zeros of the transfer function are: v ref v out v comp r 1 r 3 c 3 r 2 c 2 c 1 fb figure 8. compensation network ( ) c3 r3 2 1 f c2 c1 c2 c1 r2 2 1 f c3 r3 r1 2 1 f c2 r2 2 1 f p2 p1 z2 z1 p = ? ? ? ? + p = + p = p = ( ) ? ? ? ? + ? ? ? ? + + ? ? ? ? ? + + ? ? ? ? + + = ? ? ? ? + ? ? ? ? + = = c3 r3 1 s c2 c1 r2 c2 c1 s s c3 r3 r1 1 s c2 r2 1 s c1 r3 r1 r3 r1 sc3 1 r3 r1// sc2 1 r2 // sc1 1 v v gain out comp amp
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - n o v . , 2 0 1 2 a p w 7 0 7 3 a w w w . a n p e c . c o m . t w 1 4 the poles and zero of this transfer functions are: a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) pwm compensation (cont.) the closed loop gain of the converter can be written as: gain lc x gain pwm x gain amp figure 9. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network. using the below guidelines should give a compensation similar to the curve plotted. a stable closed loop has a -20db/ decade slope and a phase margin greater than 45 degree. 1. choose a value for r1, usually between 1k and 5k. 2. select the desired zero crossover frequency f o : (1/5 ~ 1/10) x f s >f o >f esr use the following equation to calculate r2: 3. place the first zero f z1 before the output lc filter double pole frequency f lc . f z1 = 0.75 x f lc calculate the c2 by the equation: 4. set the pole at the esr zero frequency f esr : f p1 = f esr calculate the c1 by the equation: 5. set the second pole f p2 at the half of the switching frequency and also set the second zero f z2 at the output lc filter double pole f lc . the compensation gain should not exceed the error amplifier open loop gain, check the compensation gain at f p2 with the capabilities of the error amplifier. f p2 = 0.5 x f s f z2 = f lc combine the two equations will get the following component calculations: r1 f f v v r2 lc o in osc d = 0.75 f r2 2 1 c2 lc p = 1 f c2 r2 2 c2 c1 esr - p = 1 c esr s c l s c esr s 1 gain out out 2 out lc + + + = figure 9. converter gain and frequency s lc s out lc f r3 1 c3 1 f 2 f r1 r3 c l 2 1 f p = - = p = f lc frequency(hz) g a i n ( d b ) 20log (r 2 /r 1 ) 20log ( v in / g v osc ) f z1 f z2 f p1 f p2 f esr pwm & filter gain converter gain compensation gain
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - n o v . , 2 0 1 2 a p w 7 0 7 3 a w w w . a n p e c . c o m . t w 1 5 l a y o u t c o n s i d e r a t i o n layout consideration in any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. with power devices switching at 300khz, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. as an example, consider the turn-off transition of the pwm mosfet. before turn-off, the mosfet is carrying the full load current. during turn-off, current stops flowing in the mosfet and is free-wheeling by the lower mosfet and parasitic diode. any parasitic inductance of the circuit generates a large voltage spike during the switching interval. in general, using short, wide, and printed circuit traces should minimize interconnect- ing impedances and the magnitude of voltage spike. and signal and power grounds are to be kept separating till combined using ground plane construction or single point grounding. figure 10 illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. components along the bold lines should be placed lose together. below is a check- list for your layout: - keep the switching nodes (ugate, lgate, and phase) away from sensitive small signal nodes since these nodes are fast moving signals. therefore, keep traces to these nodes as short as possible. - the traces from the gate drivers to the mosfets (ugate, lgate) should be short and wide. - place the source of the high-side mosfet and the drain of the low-side mosfet as close as possible. minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - decoupling capacitor, compensation component, the resistor dividers, boot capacitors, and ss capacitors should be close their pins. (for example, place the decoupling ceramic capacitor near the drain of the high-side mosfet as close as possible. the bulk capacitors are also placed near the drain). - the input capacitor should be near the drain of the upper mosfet; the output capacitor should be near the loads. the input capacitor gnd should be close to the output capacitor gnd and the lower mosfet gnd. - the drain of the mosfets (v in and phase nodes) should be a large plane for heat sinking. figure 10. layout guidelines vcc pvcc boot phase ugate lgate v in v out l o a d apw7073a
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - n o v . , 2 0 1 2 a p w 7 0 7 3 a w w w . a n p e c . c o m . t w 1 6 p a c k a g e i n f o r m a t i o n s o p ? 1 4 s y m b o l min. max. 1.75 0.10 0.17 0.25 0.25 a a1 c d e e1 e h l millimeters b 0.31 0.51 sop-14 0.25 0.50 0.40 1.27 min. max. inches 0.069 0.004 0.012 0.020 0.007 0.010 0.010 0.020 0.016 0.050 0 0.010 1.27 bsc 0.050 bsc a2 1.25 0.049 0 8 0 8 l view a 0 . 2 5 seating plane gauge plane note: 1. follow jedec ms-012 ab. 2. dimension ? d ? does not include mold flash, protrusions or gate burrs. mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. dimension ? e ? does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 10 mil per side. 3.80 5.80 8.55 4.00 6.20 8.75 0.337 0.344 0.228 0.244 0.150 0.157 d e b e 1 e see view a c h x 4 5 a a 1 a 2
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - n o v . , 2 0 1 2 a p w 7 0 7 3 a w w w . a n p e c . c o m . t w 1 7 application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 16.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 16.0 ? 0.30 1.75 ? 0.10 7.50 ? 0.10 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 sop - 14 4.0 ? 0.10 8.0 ? 0.10 2.0 ? 0.10 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0. 40 6.40 ? 0.20 9.00 ? 0.20 2.10 ? 0.20 (mm) c a r r i e r t a p e & r e e l d i m e n s i o n s d e v i c e s p e r u n i t package type unit quantity sop - 14 tape & reel 2500 a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 h t1 a d
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - n o v . , 2 0 1 2 a p w 7 0 7 3 a w w w . a n p e c . c o m . t w 1 8 t a p i n g d i r e c t i o n i n f o r m a t i o n user direction of feed s o p ? 1 4 c l a s s i f i c a t i o n p r o f i l e
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - n o v . , 2 0 1 2 a p w 7 0 7 3 a w w w . a n p e c . c o m . t w 1 9 c l a s s i f i c a t i o n r e f l o w p r o f i l e s profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spec ified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined a s a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ tj=125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma r e l i a b i l i t y t e s t p r o g r a m
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - n o v . , 2 0 1 2 a p w 7 0 7 3 a w w w . a n p e c . c o m . t w 2 0 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8

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Price & Availability of APW7073AKE-TRG

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